Pixel Readout Chip Status

MARCH, 2003

The development of the BTeV readout chip is nearing completion. A series of tests of prototype chips implemented in two different commercial 0.25 micron CMOS processes have verified the functionality of all of the circuit blocks that make up the readout chip. Devices have been irradiated to 87 Mrad (~3 x 10^15 MIPs), a much higher dose than expected in ten years of running. This dose resulted in minimal threshold shifts and only minor changes to noise level. The rate of single-event upsets has been measured and proven to be well within acceptable limits.

Twenty-two 8-inch wafers of full-size "FPIX2" readout chips, including essentially all of the features envisioned for the final device, were received in January 2003. Tests performed in February indicate that the chip operates as designed. A large number of FPIX2 readout chips will soon be bump-bonded to sensors of various sizes and tested both on the bench and in a test beam at Fermilab.

APRIL, 2002

Pre-prototype readout chips in deep-submicron technology (0.25 micron minimum feature size) have demonstrated their viability. Test devices of the near-final data serializer and other peripheral components are being submitted now. A full-size readout chip in this technology is the next major step after demonstration of this periphery and a modification to the front end system to achieve lower threshold dispersion.

Devices have been irradiated to 87 MRad (~3 x 10^15 MIPs) with minimal threshold shifts and only minor changes to noise level. The rate of single-event upsets and other operational problems have been proven to be well within acceptable levels, well beyond ten years operation at nominal luminosity.

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